Job expirat
The Design Verification Engineer is responsible for the definition, design implementation and documentation of the verification environment for digital projects.
Work on the test plan generation.
Implement elements of the verification environment.
Run tests and regressions.
Analyzes log files using self-built or existing scripts.
Contribute to finding bugs in the RTL code.
Skills and experience
• B.S or higher in Electrical Engineering or equivalent degree,
• Minimum 3 years experience in Design Verification,
• Excellent knowledge of a Hardware Verification Language (preferred System Verilog),
• Experience with logic design and RTL coding using a Hardware Description Language (Verilog or VHDL)
• Strong knowledge of computer arhitectures, digital signal processing and other structures, commonly used in VLSI design,
• Experience with a version control software,
• Experience with a scripting language
• Experience with Unix, at user level.
• competitive salary
• medical insurance
• meal tickets
• training in USA