Job expirat
Responsible for using logic simulation or formal verification techniques to validate that the hardware DUV (design under verification) functions according to specifications. Specifications can be given in the form of the defined instruction-set architecture, a functional bus-interface or protocol specification, or a micro architectural specification of the DUV. Verification on a functional unit requires the engineer to program a test bench and checkers to validate the DUV results. Verification on the architecture or bus-interface level requires deep knowledge of the specification and the application of test-generation tools. Formal verification requires the application of formal tools like model checkers.
Hardware:
Knowledge of Digital Logic Design
Software:
C/C++ (mandatory)"
Hardware:
Verilog;
VHDL;
System Verilog;
Verification languages such as Specman, Vera or System Verilog;
Experience with Functional Verification and/or Formal Verification;
Software:
Assembly
Scripting languages such as PERL and/or TCL
Working knowledge of OOP techniques
Knowledge in UNIX and/or Linux operating systems
Education in Electrical Engineering BSc. / MSc. or PhD.
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