Job expirat
Participate in the design of a high-performance (low-power) system CPU. Work with Logic Design teams to define a block and take it from RTL, draw schematics using logic gates from either a standard library or individually created, optimize above CMOS schematic to meet macro design guideline targets; i.e. cycle time, testability, slew limits, drive strengths, etc. Perform feasibility spice simulations, create, debug and optimize layout and perform the necessary backend checks. Be responsible for delivering the block to work under a tight timing (and power) budget. Additionally, may be responsible for taking RTL as input and submitting to an automated synthesis process to create a Boolean equivalent CMOS schematic. This schematic is then sent thru an auto place and auto route process in order to obtain an equivalent physical design implementation of the RTL.
Experience in Digital CMOS custom design;
Experience in processor design from a circuit level;
Reasonable familiarity with CPU/SOC microarchitecture;
Close familiarity with custom EDA tools (Cadence schematic and layout tools);
Design experience in deep submicron technologies and basic device physics;
Design experience in low power methodology;
Design experience in dynamic circuits;
Ability to work in a team, deliver tasks."
"Custom methodology development;
Scripting skills (SKILL/PERL/TCL);
RTL coding experience;
SRAM/Cache design experience;
Education in Electrical Engineering BSc. / MSc. or PhD.
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