Job expirat
Participate in the design of a high-performance (low-power) system on a chip/CPU with emphasis on high performance (low power) memory design. Work extensively with the architecture teams and logic team to define the various RAM components and take it from definition, write and debug RTL, draw schematics, perform feasibility spice simulations, create layout and perform the necessary back end checks. Optimize above CMOS schematic and layout to meet array design guideline targets; i.e. cycle time, testability, slew limits, etc. Be responsible for delivering the block to work under a tight timing (and power) budget.
Experience in cache/SRAM memory design;
Reasonable familiarity with CPU/SOC microarchitecture;
Close familiarity with custom EDA tools (Cadence schematic and layout tools);
Design experience in deep submicron technologies in and basic device physics;
Design experience in dynamic circuits;
Ability to work in a team, deliver tasks."
"Understand memory hierarchy for a processor system;
Design experience in low power methodology;
Scripting skills (SKILL/PERL/TCL);
RTL coding experience;
Experience in Digital CMOS custom design;
Education in Electrical Engineering BSc. / MSc. or PhD.
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